1. Field of the Invention
The present invention relates to a pixel array layout. More particularly, the present invention relates to a pixel array layout having a pre-discharge conductive layer.
2. Description of Related Art
Owing to diversity of information equipment, demands for flat panel displays (FPDs) are increased day by day. With the current market trend of compactness and low power consumption, cathode ray tube (CRT) displays have been gradually replaced by the FPDs. At present, the FPDs can be roughly categorized into plasma display panels (PDPs), liquid crystal displays (LCDs), vacuum fluorescent displays, field emission displays, electro-chromic displays, organic light-emitting displays (OLEDs), and so forth. In comparison with other FPD techniques, the OLEDs have a tremendous application potential to become the mainstream FPDs in the next generation due to various advantages including self-luminescence, no viewing-angle dependence, low power consumption, simple fabrication, low costs, low working temperature, high response speed, and full-color display.
Nowadays, organic light-emitting materials are already successfully applied to the FPDs, and the OLEDs can be divided into passive matrix OLEDs and active matrix OLEDs. Generally, the main difference between the passive matrix OLED and the active matrix OLED lies in that each pixel in the active matrix OLED has a storage capacitor for ensuring favorable display quality. Since active matrix OLED techniques are conducive to development of displays towards great dimension and high resolution, the active matrix OLED draws more attention than the passive matrix OLED does.
In a conventional active matrix OLED, a driving circuit in each pixel unit normally has a 2T1C structure, i.e., two transistors and one storage capacitor, so as to control a driving current flowing into each pixel unit. To stabilize the driving current, a 3T1C structure, i.e., three transistors and one storage capacitor, is adopted to form the driving circuit in the pixel unit according to the related art, as shown in FIG. 1.
FIG. 1 is a schematic view of a conventional driving circuit having the 3T1C structure. Referring to FIG. 1, the conventional driving circuit 100 having the 3T1C structure includes a switching transistor TFT1, a driving transistor TFT2, a pre-discharge transistor TFT3, and a storage capacitor Cst. The switching transistor TFT1 has a first gate G1, a first source S1, and a first drain D1. The first gate G1 is electrically connected to one scan line SLn, and the first drain D1 is electrically connected to one data line DL. The driving transistor TFT2 has a second gate G2, a second source S2, and a second drain D2. The second drain D2 is electrically connected to a voltage or a current source VDD, and the second source S2 is electrically connected to a pixel electrode P. The pre-discharge transistor TFT3 has a third gate G3, a third source S3, and a third drain D3. The third gate G3 is electrically connected to the preceding scan line SLn-1, and the third source S3 is electrically connected to a metal pre-discharge conductive layer 102. Besides, the storage capacitor Cst has a first electrode E1 and a second electrode E2. The first electrode E1, the first source S1, the second gate G2, and the third drain D3 are electrically connected together, and the second electrode E2 is electrically connected to the voltage source VDD.
It can be learned from FIG. 1 that the switching transistor TFT1 is used for an address operation and for determining the degree to which the driving transistor TFT2 is turned on. Besides, the driving transistor TFT2 controls the driving current passing through an organic light-emitting diode 104. The pre-discharge transistor TFT3 is used for a pre-discharging operation, so as to avoid offset of a threshold voltage Vth. In detail, when a high voltage is input to the second scan line SLn, the switching transistor TFT1 connected to the second scan line SLn is turned on. Here, the data line DL can transmit image signals to the second gate G2 of the driving transistor TFT2 through the switching transistor TFT1, so as to determine the degree to which the driving transistor TFT2 is turned on. As such, the voltage source VDD is able to supply a current corresponding to the image signals to the organic light-emitting diode 104 through the driving transistor TFT2, such that the organic light-emitting diode 104 can ensure the images to be displayed at correct grey levels. When the switching transistor TFT1 is turned off, the voltage of the second gate G2 can be maintained by the storage capacitor Cst, such that the driving current continuously passes through the driving transistor TFT2 and the organic light-emitting diode 104.
When a high voltage is input to the first scan line SLn-1, the pre-discharge transistor TFT3 connected to the first scan line SLn-1 is turned on. Here, charges stored in the storage capacitor Cst are released by the pre-discharge transistor TFT3 and output from the metal pre-discharge conductive layer 102, so as to avoid offset of the threshold voltage Vth of the transistor TFT2.
FIG. 2A is a schematic top view of a conventional pixel array layout. FIG. 2B is a partial enlarged view of an area A of the conventional pixel array layout 200 depicted in FIG. 2A. Referring to FIGS. 2A and 2B, the conventional pixel array layout 200 includes a substrate 202, a plurality of scan lines SL disposed on the substrate 202, a plurality of data lines DL disposed on the substrate 202, a plurality of pixel units 204 disposed on the substrate 202, and a metal pre-discharge conductive layer 102. Here, each of the pixel units 204 includes a pixel electrode P and a driving circuit 100. The metal pre-discharge conductive layer 102 is grounded or coupled to a negative voltage and crosses over a plurality of pixel units 204, so as to electrically connect the pre-discharge transistor TFT3 (shown in FIG. 1) disposed in each of the pixel units 204.